1. Field of the Invention
The present invention relates to a method of manufacturing memory. More particularly, the present invention relates to a flash memory device and manufacturing method thereof.
2. Description of the Related Art
Flash memory is a type of non-volatile memory that permits multiple data writing, reading and erasing operations. The stored data will be retained even power off. With all these advantages, flash memory has become one of the most widely adopted non-volatile memories for personal computer and electronic equipment.
FIG. 1 is a schematic cross-sectional view of a conventional flash memory device. As shown in FIG. 1, the flash memory mainly comprises a substrate 100, a tunneling oxide layer 102, a floating gate 104, an inter-polysilicon dielectric layer 106, a control gate 108 and a pair of source/drain regions 120. The floating gate 104 is disposed on the substrate 100. The floating gate 104 consists of a patterned conductive layer and spacers on each sidewall thereof. The tunneling oxide layer 102 is disposed between the substrate 100 and the floating gate 104. The control gate 108 is disposed over the floating gate 104 and the inter-polysilicon dielectric layer 106 is disposed between the control gate 108 and the floating gate 104. The tunneling oxide layer 102, the floating gate 104, the inter-polysilicon dielectric layer 106 and the control gate 108 together form the stack gate structure 110. Each source/drain region 120 is disposed in the substrate 100 on each side of the stack gate structure 110.
As the line width of semiconductor devices continue to decrease, the dimension of each device is also reduced. As a result, there is a significant drop in the coupling ratio between the control gate and the floating gate of the flash memory device.
In recent years, an improved method of manufacturing the flash memory has been developed. A first conductive pattern is formed over a substrate and then a second conductive pattern with a larger area is formed over the first conductive pattern. Since the first and the second conductive patterns can serve as the floating gate of the flash memory device, the coupling ratio between the floating gate and the control gate is increased.
Although the aforementioned technique of increasing the area of the floating gate can improve the coupling ratio between the floating gate and the control gate, the larger area occupied by the second conductive pattern set a limit on the ultimate level of integration for the devices. Moreover, the step of forming the second conductive pattern over the first conductive pattern increases the complexity of manufacturing the memory device. In other words, the process goes against our goal of miniaturizing devices and minimizing the number of fabrication steps.